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| DS3013 - 2.2 ZN448/ZN449 8-BIT MICROPROCESSOR COMPATIBLE A-D CONVERTER The ZN448 and ZN449 are 8-bit successive approximation A-D converters designed to be easily interfaced to microprocessors. All active circuitry is contained on-chip including a clock generator and stable 2.5V bandgap reference, control logic and double buffered latches with reference. Only a reference resistor and capacitor, clock resistor and capacitor and input resistors are required for operation with either unipolar or bipolar input voltage. BUSY (END OF CONVERSION) RD (OUTPUT ENABLE) CLOCK WR (START CONVERSION) REXT VIN VREF IN 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) +VCC (+5V) FEATURES s s s s s s s Easy Interfacing to Microprocessor, or operates as a 'Stand-Alone' Converter Fast: 9 microseconds Conversion time Guaranteed Choice of Linearity: 0.5 LSB - ZN448, 1 LSB - ZN449 On-Chip Clock Choice of On-Chip or External Reference Voltage Unipolar or Bipolar Input Ranges Commercial Temperature Range VREF OUT GROUND ZN448/9E (DP18) BUSY (END OF CONVERSION) RD (OUTPUT ENABLE) CLOCK WR (START CONVERSION) REXT 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) +VCC (+5V) ORDERING INFORMATION Device type ZN448E ZN449D ZN449E Linearity error (LSB) 0.5 1 1 Operating temperature 0C to +70C 0C to +70C 0C to +70C Package DP18 MP18 DP18 VIN VREF IN VREF OUT GROUND ZN449D (MP18) Fig.1 Pin connection - top view COMPARATOR ANALOGUE INPUT VREF IN 6 + 5 REXT 7 8-BIT DAC - VREF OUT 8 2.5V REFERENCE CLOCK GENERATOR 3 CK RC OR EXT CLOCK GROUND 9 SUCCESSIVE APPROXIMATION REGISTER INTERFACE AND CONTROL LOGIC 4 WR 1 BUSY VCC (+5V) 10 3-STATE BUFFERS 2 RD 11 DB7 12 13 14 15 16 17 18 DB0 Fig.2 System diagram ZN448/9 ABSOLUTE MAXIMUM RATINGS Supply voltage VCC Max. voltage, logic and VREF input Operating temperature range Storage temperature range +7 +VCC 0C to +70C (MP and DP package) -55C to +125C ELECTRICAL CHARACTERISTICS (at VCC = 5V, Tamb = 25C and fCLK = 1.6MHz unless otherwise specified). Parameter ZN448 Linearity error Differential linearity error Zero transition (0000000000000001) Full-scaletransition (11111110 11111111) ZN449 Linearity error Differential linearity error Zero transition (0000000000000001) Full-scaletransition (11111110 11111111) All Types Resolution Linearity temperature coefficient Differential linearity temperature coefficient Full-scale temperature coefficient Zero temperature coefficient Reference input range Supply voltage Supply current Power consumption Comparator Input current Input resistance Tail current Negative supply Input voltage On-chip reference Output voltage ZN448 ZN449 Slope resistance VREF temperature coefficient Reference current Min. Typ. Max. 0.5 0.75 18 2.555 Units LSB LSB mV V Conditions 12 2.545 15 2.550 DP package VREF = 2.560V 7 10 2.542 12 15 2.550 1 1 17 20 2.558 LSB LSB mV mV V MP package DP package VREF = 2.560V 8 1 4.5 - 3 6 2.5 8 5 25 125 3 5.5 40 200 bits ppm/C ppm/C ppm/C V/C V V mA mW A k A V V 25 -3 -0.5 1 100 65 -5 - 150 -30 +3.5 VIN = +3V, REXT = 82k V - = -5V 2.520 2.520 4 2.550 2.550 0.5 50 - 2.580 2.600 2 15 V ppm/C mA RREF = 390 CREF = 47 2 ZN448/9 ELECTRICAL CHARACTERISTICS (Cont.) Parameter Clock On-chip clock frequency Clock frequency temperature coefficient Clock resistor Maximum external clock frequency Clock pulse width High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL Logic (over operating temperature range) Convert input High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL RD input High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL High level output voltage VOH Low level output voltage VOL High level output current IOH Low level output current IOL Three-state disable output leakage Input clamp diode voltage RD input to data output Enable/disable delay times TE1 TE0 TD1 TD0 Convert pulse width tWR WR input to BUSY output Min. Typ. Max. Units MHz %/C k MHz ns V V A A Conditions 0.9 500 4 - +0.5 - 1 2 1 0.8 800 -500 VIN = +4V, VCC = MAX VIN = +0.8V, VCC = MAX 2 - 300 10 0.8 - V V A A VIN = +2.4V, VCC = MAX VIN = +0.4V, VCC = MAX 2 2.4 180 60 80 60 200 - +150 -300 180 210 80 110 80 - 0.8 0.4 -100 1.6 2 -1.5 250 260 100 140 100 250 V V A A V V A mA A V ns ns ns ns ns ns ns VIN = +2.4V, VCC = MAX VIN = +0.4V, VCC = MAX IOH = +2.4V, VCC = MAX IOL = +0.4V, VCC = MAX VOUT = +2V GENERAL CIRCUIT OPERATION The ZN448/9 utilises the successive approximation technique. Upon receipt of a negative-going pulse at the WR input the BUSY output goes low, the MSB is set to 1 and all other bits are set to 0, which produces an output voltage of VREF/2 from the DAC. This is compared to the input voltage VIN; a decision is made on the next negative clock edge to reset the MSB to 0 if VREF VREF < VIN or leave it set to 1 if 2 2 < VIN. During a conversion the RD input will normally be held high to keep the three-state buffers in their high impedance state. Data can be read out by taking RD low, thus enabling the three-state output. Readout is non-destructive. CONVERSION TIMING The ZN448/9 will accept a low-going CONVERT pulse, which can be completely asynchronous with respect to the clock, and will produce valid data between 7.5 and 8.5 clock pulses later depending on the relative timing of the clock and CONVERT signals. Timing diagrams for the conversion are shown in Fig.3. The converter is cleared by a low-going CONVERT pulse, which sets the most significant bit and results all the other bits and the BUSY flag. Whilst the CONVERT input is low the MSB output of the DAC is continuously compared with the analogue input, but otherwise the converter is inhibited. Bit 2 is set to 1 on the same clock edge, producing an output VREF VREF VREF from the DAC of or + depending on the state 4 2 4 of the MSB. This voltage is compared to VIN and on the next clock edge a decision is made regarding bit 2, whilst bit 3 is set to 1. This procedure is repeated for all eight bits. On the eighth negative clock edge BUSY goes high indicating that the conversion is complete. 3 ZN448/9 After the CONVERT input goes high again the MSB decision is made and the successive approximation routine runs to completion. The CONVERT pulse can be as short as 200ns; however the MSB must be allowed to settle for at least 550ns before the MSB decision is made. To ensure that this criterion is met even with short CONVERT pulses the converter waits, after the CONVERT input goes high, for a rising clock edge followed by a falling clock edge, the MSB decision being taken on the falling clock edge. This ensures that the MSB is allowed to settle for at least half a clock period, or 550ns at maximum clock frequency. The CONVERT input is not locked out during a conversion and if it is oulsed low at any time the converter will restart. The BUSY output goes high simultaneously with the LSB decision, at the end of a conversion indicating data valid. Note that if the three-state data outputs are enabled during a conversion the valid data will be available at the outputs after the rising edge of the BUSY signal. If, however the outputs are not enabled until after BUSY goes high then the data will be subject to the propagation delay of the three-state buffers. (See under DATA OUTPUTS). Fig.3 ZN448/9 timing diagram 4 ZN448/9 If a free-running conversion is required, then the converter can be made to cycle by inverting the BUSY output and feeding it to WR. To ensure that the converter starts reliably after powerup an initial start pulse is required. This can be ensured by using a NOR gate instead of an inverter and feeding it with a positive-going pulse which can be derived from a simple RC network that gives a single pulse when power is applied, as shown in Fig.4a. The ADC will complete a conversion on every eighth clock pulse, with the BUSY output going high for a period determined by the propagation delay of the NOR gate, during which time the data can be stored in a latch. The time available for storing data can be increased by inserting delays into the inverter path. A timing diagram for the continuous conversion mode is shown in Fig.3b. As the BUSY output uses a passive pull-up the rise time of this output depends on the RC time constant of the pull-up resistor and load capacitance. In the continuous conversion mode the use of a 4k7 external pull-up resistor is recommended to reduce the risetime and ensure that a logic 1 level is reached. Fig.4a Circuit for continuous conversion Fig.4b Timing for continuous conversion DATA OUTPUTS The data outputs are provided with three-state buffers to allow connection to a common data bus. An equivalent circuit is shown in Fig.5. Whilst the RD input is high both output transistors are turned off and the ZN448/9 presents only a high impedance load to the bus. When RD is low the data outputs will assume the logic states present at the outputs of the successive register. A test circuit and timing diagram for the output enable/disable delays are given in Fig.6. 5 ZN448/9 VCC 500 20k BITS 1-8 (PINS 11-18) 10k RD (PIN 2) GROUND Fig.5 Data output Fig.6 Output enable/disable delays 6 ZN448/9 BUSY OUTPUT The BUSY output, shown in Fig.7, utilises a passive pull-up for CMOS/TTL compatibility. This allows up to four BUSY outputs to be wire-ANDed together to form a common interrupt line. Fig.7 BUSY output ON-CHIP CLOCK The on-chip clock operates with only a single external capacitor connected between pin 3 and ground, as shown in Fig.8a. A graph of typical oscillator frequency versus capacitance is given in Fig.9. The oscillator frequency may be trimmed by means of an external resistor in series with the capacitor, as shown in Fig.8b. However, due to processing tolerance, the absolute clock frequency may vary considerably between devices. For optimum accuracy and stability of the oscillator frequency, it may be possible to use a crystal or ceramic resonator with suitable load components, as shown in Fig.8c. The final option is to overdrive the oscillator input with an external clock signal from a TTL or CMOS gate, as shown in Fig.8d. 3 OSC 2k MAX 3 9 GND 9 a) Fixed/variable capacitor b) Fixed capacitor + variable resistor VCC 1.2k 3 4.7k D 2200pF D 1MHz Xtal D56pF 9 D Load circuit to suit device used 3 c) Crystal or resonator d) External TTL or CMOS drive Fig.8 Clock circuit external components 7 ZN448/9 1MHz 100kHz 10kHz 1kHz 10p 100p 1n 10n 100n Fig.9 Typical clock frequency v CCK (RCK = 0) ANALOG CIRCUITS D-A converter The converter is of the voltage switching type and uses an R2R ladder network as shown in Fig.10. Each element is connected to either 0V or VREF IN by transistor voltage switches specially designed for low offset voltage (1mV). A binary weighted voltage is produced at the output of the R2R ladder. D to A output = n (VREF IN -VOS) + VOS 256 where n is the digital input to the D-A from the successive approximation register. VOS is a small offset voltage that is produced by the device supply current flowing in the package lead resistance. The offset will normally be removed by the setting up procedure and since the offset temperature coefficient is low (8V/C) the effect on accuracy will be neglible. The D-A output range can be considered to be 0 - VREF IN through an output resistance R (4k). R(4k) R R R D TO A OUTPUT 2R VREF IN (PIN 7) 2R 2R 2R 2R VOLTAGE SWITCHES 0 VOLTS (PIN 9) VOS DB0 DB1 DB6 DB7 Fig.10 R-2R ladder network 8 ZN448/9 REFERENCE (a) Internal reference The internal reference is an active bandgap circuit which is equivalent to a 2.5V Zener diode with a very low slope impedance (Fig.11). A Resistor (RREF) should be connected between pins 8 and 10. The recommended value of 390 will supply a nominal reference current of (5 - 2.5)/0.39=6.4mA. A stabilising/ decoupling capacitor, CREF (47), is required between pins 8 and 9. For internal reference operation VREF OUT (pin 8) is connected to VREF IN (pin 7). UP to five ZN448/9's may be driven from one internal reference, there being no need to reduce RREF. This useful feature saves power and gives excellent gain tracking between the converters. Alternatively the internal reference can be used as the reference voltage for other external circuits and can source or sink up to 3mA. (b) External reference If required an external reference in the range +1.5 to +3.0V may be connected to VREF IN. The slope resistance of such a reference source should be less than 2.5, where n is the n number of converters supplied. VCC +5V (PIN 10) RREF (390) VREFOUT (PIN 8) CREF (0.47) GROUND (PIN 9) Fig.11 Internal voltage reference RATIOMETRIC OPERATION If the output from a transducer varies with its supply then an external reference for the ZN4448/9 should be derived from the same supply. The external reference can vary from +1.5 to +3.0V. The ZN448/9 will operate if VREF IN is less than +1.5V but reduced overdrive to the comparator will increase its delay and so the conversion time will need to be increased. COMPARATOR The ZN448/9 contains a fast comparator, the equivalent input circuit of which is shown in Fig.12. A negative supply voltage is required to supply the tail current of the comparator. However as this is only 25 to 150A and need not be well stabilised it can be supplied by a simple diode pump circuit driven from the BUSY output. 9 ZN448/9 +5V PIN 10 6k 6k + TO LOGIC HIGH = 'RETAIN BIT' AIN RIN 4k VIN PIN 6 4k D TO A OUTPUT (O - VREFIN) PIN 5 REXT IEXT V- Fig.12 Comparator equivalent circuit Fig.13 Diode pump circuits to supply comparator tail current 10 ZN448/9 Several suitable circuits are shown in Fig.13. The principle of operation is the same in each case. Whilst the BUSY output is high, capacitor C1 is charged to about 4-4.5V. During a conversion the BUSY output goes low and the upper end of C1 is thus also pulled low. The lower end of C1 therefore applies about -4V to R2, thus providing the tail current for the comparator. The time constant R2. C1 is chosen according to the clock frequency so that droop of the capacitor voltage is not significant during a conversion. The constraint on using this type of circuit is that C1 must be recharged whilst the BUSY output is high. If the BUSY output is high for greater than one converter clock period then the circuit of Fig.13a will suffice. If this is not the case, for example, in the continuous conversion mode, then the circuits of Figs. 13b and 13c are recommended, since these can pump more current into the capacitor. Where several ZN448/9's are used in a system the selfoscillating diode pump circuit Fig.14 is recommeded. Alternatively, if a negative supply is available in the system then this may be utilised. A list of suitable resistor values for different supply voltages is given in Table 1. 330 5V 470 100n IN914 -3.5V 22n IN914 100n Fig.14 Diode pump circuit to supply comparator tail current for up to five ZN448/9's V - (volts) 3 5 10 12 15 20 25 30 Table 1 REXT (k) 47 82 150 180 220 330 390 470 11 ZN448/9 ANALOG INPUT RANGES The basic connection of the ZN448/9 shown in Fig.15 has an analogue input range 0 to VREF IN which, in some applications, may be made available from previous signal conditioning/ scaling circuits. Input voltage ranges greater than this are accommodated by providing an attenuator on the comparator input, whilst for smaller input ranges the signal must be amplified to a suitable level. Bipolar input ranges are accommodated by off-setting the analogue input input range so that the comparator always sees a positive input voltage. DIGITAL OUTPUTS LSB DB0 1 2 3 4 5 6 MSB DB7 VCC (+5V) 18 17 16 15 14 13 12 11 10 RREF (390) 1 2 3 4 5 VIN REXT (82k) RIN (4k) 6 7 8 9 CREF (47) BUSY RD CK WR V(-5V) AIN VREFIN VREFOUT GND (0V) NOMINAL AIN RANGE = 0 TO VREFIN Fig.15 External components for basic operation 12 ZN448/9 UNIPOLAR OPERATION The general connection for unipolar operation is shown in Fig.16. The values of R1 and R2 are chosen so that VIN = VREF IN when the analog input (AIN) is at full-scale. The resulting full-scale range is given by: AINFS = 1 + R1 R2 , VREF IN = G.VREF IN. To match the ladder resistance R1/R2 (RIN) = 4k. The required nominal values of R1 and R2 are given by R1 = 4Gk, R2 = 4G k G-1 AIN VREF IN 1M ZERO ADJUST R1 680k VIN 7 6 ZN448/9 9 GROUND R2 Fig.16 General unipolar input connections Using these relationships a table of nominal values of R1 and R2 can be constructed for VREF IN = 2.5V. Input range +5V +10V G 2 4 R1 8k 16k R2 8k 5.33k Zero adjustment Due to offsets in the DAC and comparator the zero (0 to 1) code transition would occur with typically 15mV applied to the comparator input, which correpsonds to 1.5LSB with a 2.56V reference. Zero adjustment must therefore be provided to set the zero transition to its correct value of +0.5LSB or 5mV with a 2.56V reference. This is achieved by applying an adjustable positive offset to the comparator input via P2 and R3. The values shown are suitable for all input ranges greater than 1.5 times VREF IN. Practical circuit values for +5 and +10V input ranges are given in Fig.17, which incorporates both zero and gain adjustments. Gain adjustment Due to tolerance in R1 and R2, tolerance in VREF and the gain (full-scale) error of the DAC, some adjustment should be incorporated into R1 to calibrate the full-scale of the converter. When used with the internal reference and 2% resistors a preset capable of adjusting R1 by at least 5% of its nominal value is suggested. 13 ZN448/9 AIN VREF IN AIN VREF IN P1 5k GAIN ADJUST 1M ZERO ADJUST P2 P1 10k GAIN ADJUST 1M ZERO ADJUST P2 R1 5k6 680k R3 R1 11k 680k R3 TO PIN 6 R2 8k2 2% RESISTORS 20% POTENTIOMETERS R2 5k6 TO PIN 6 +5V FULL-SCALE +10V FULL-SCALE Fig.17 Unipolar operation component values Unipolar adjustment prodedure (i) Apply continuous convert pulses at intervals long enough to allow a complete conversion and monitor the digital outputs. (ii) Apply full-scale minus 1.5LSB to AIN and adjust off-set until the bit 8 (LSB) output just flickers between 0 and 1 with all other bits at 0. (iii) Apply 0.5LSB to AIN and adjust zero until 8 bit just flickers between 0 and 1 with all other bits at 1. Unipolar setting up points Input range, +FS +5V +10V 1LSB = FS 256 0.5LSB 9.8mV 19.5mV FS - 1.5LSB 4.9707V 9.9414V Bipolar logic coding Analogue input (AIN) (Nominal code centre value) FS - 1LSB FS - 2LSB 0.75FS 0.5FS + 1LSB 0.5FS 0.5FS - 1LSB 0.25FS 1LSB 0 Output code (offset binary) 11111111 11111110 11000000 10000001 10000000 01111111 01000000 00000001 00000000 14 ZN448/9 BIPOLAR OPERATION For bipolar operation the input to the ZN448/9 is offset by half full-scale by connecting a resistor R3 between VREF IN and VIN (Fig.18). AIN VREF IN R1 R3 VIN 7 6 ZN448/9 9 GROUND R2 Fig.18 Basic bipolar input connection When AIN = -FS, VIN needs to be equal to zero. When AIN = +FS, VIN needs to be equal to VREF IN. If the full-scale range is G. VREF IN then R1 = (G - 1). R2 and R1 = G. R3 fulfil the required conditions. To match the ladder resistance, R1/R2/R3 (=RIN) = 4k. Thus the nominal values of R1, R2, R3 are given by R1 = 8 Gk, R2 = 8G/(G - 1)k, R3 = 8k. A bipolar range of VREF IN (which corresponds to the basic unipolar range 0 to +VREF IN) results if R1 = R3 = 8k and R2 = . Assuming the VREF IN = 2.5V the nominal values of resistors for 5 and 10V input ranges are given in the following table. Input range +5V +10V G 2 4 R1 16k 32k R2 16k 10.66k R3 8k 8k Minus full-scale (offset) is set by adjusting R1 about its nominal value relative to R3. Plus full-scale (gain) is set by adjusting R2 relative to R1. Practical circuit realisations are given in Fig.19. Note that in the 5V case R3 has been chosen as 7.5k (instead of 8.2k) to obtain a more symmetrical range of adjustment using standard potentiometers. 15 ZN448/9 AIN VREF AIN VREF 5k OFFSET ADJUST 7k5 10k OFFSET ADJUST 8k2 13k 27k TO PIN 6 5k GAIN ADJUST 2% RESISTORS 20% POTENTIOMETERS 13k 8k2 5k GAIN ADJUST TO PIN 6 5VOLTS FULL SCALE 10VOLTS FULL SCALE Fig.19 Bipolar operation component values Bipolar adjustment prodedure (i) Apply continuous SC pulses at intervals long enough to allow a complete conversion and monitor the digital outputs. (ii) Apply -(FS -0.5LSB) to AIN and adjust off-set until the bit 8 (LSB) output just flickers between 0 and 1 with all other bits at 0. (iii) Apply +(FS -1.5LSB) to AIN and adjust gain until the 8 bit just flickers between 0 and 1 with all other bits at 1. (iv) Repeat step (ii). Bipolar setting up points Input range, FS +5V +10V 1LSB =2FS 256 -(FS -0.5LSB) -4.9805V -9.9609V +(FS -1.5LSB) +4.9414V +9.8828V Bipolar logic coding Analogue input (AIN) (Nominal code centre value) +(FS - 1LSB) +(FS - 2LSB) +0.5FS +1LSB 0 -1LSB -0.5FS -(FS - 1LSB) -FS Output code (offset binary) 11111111 11111110 11000000 10000001 10000000 01111111 01000000 00000001 00000000 16 ZN448/9 17 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. 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Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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